`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    23:26:26 08/11/2013 
// Design Name: 
// Module Name:    OnBoardSevenSeg 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module OnBoardSevenSeg(input  clk,
	 input reset,
	 input enable,
	 input [3:0] address,
    input [31:0] dataIn,
	 output [31:0] dataOut,
	 input write,
	 output done,
	 output interrupt,
	 input clk_50,
	 output [6:0] segs,
	 output dot,
	 output [3:0]anode
    );
	 
	 parameter ON_BOARD_SEVEN_SEG_HEX_CONTROLLER_ID = 32'hA520103A;
	 
	 assign done = 1;
	 assign interrupt = 0;
	 
	 
	 //controller stuff
	 
	 reg [3:0]digitOn;
	 
	 
	 reg [19:0] data;
	 always @(posedge clk) begin
		if(reset) {digitOn, data}<= {4'b0, 20'b0};
		else begin
			if(address == 4'd0 & write & enable) {digitOn, data} <= {dataIn[3:0], data};
			else if(address == 4'd1 & write & enable) begin
				digitOn <= digitOn;
				data[3:0] <= dataIn[20] ? dataIn[3:0] : data[3:0]; //setting digit 1
				data[7:4] <= dataIn[21] ? dataIn[7:4] : data[7:4]; //setting digit 2
				data[11:8] <= dataIn[22] ? dataIn[11:8] : data[11:8]; //setting digit 3
				data[15:12] <= dataIn[23] ? dataIn[15:12] : data[15:12]; //setting digit 4
				data[19:16] <= dataIn[23:20] ? dataIn[19:16] : data[19:16]; //setting dots
			end
			else {digitOn, data} <= {digitOn, data};
		end
	 end
	 
	 
	 reg [31:0] dataOutReg;
	 assign dataOut = dataOutReg;
	 
	 always @(*) begin
		if(enable & ~write) begin
			case(address)
				4'h0: dataOutReg = {28'b0, digitOn};
				4'h1: dataOutReg = {12'b0, data};
				4'hF: dataOutReg = ON_BOARD_SEVEN_SEG_HEX_CONTROLLER_ID;
			endcase
		end
		else dataOutReg = 32'b0;
	 end
	 
	 
	 
	 //seven seg displaying stuff
	 
	 reg [13:0] count;//14
	 reg [1:0] select;
	 
	 always @(posedge clk) begin
		if(count == 14'b0) select  <= select + 1;
		else select <= select;
		count <= count + 1;
	 end
	 
	 reg enableDigit;
	 
	 reg [3:0] selectedData;
	 reg [3:0] anReg;
	 always @(*) begin
		case(select)
			2'd0: selectedData = data[3:0];
			2'd1: selectedData = data[7:4];
			2'd2: selectedData = data[11:8];
			2'd3: selectedData = data[15:12];
		endcase
		case(select)
			2'd0: anReg = 4'b0111;
			2'd1: anReg = 4'b1011;
			2'd2: anReg = 4'b1101;
			2'd3: anReg = 4'b1110;
		endcase
		case(select)
			2'd0: enableDigit = digitOn[0];
			2'd1: enableDigit = digitOn[1];
			2'd2: enableDigit = digitOn[2];
			2'd3: enableDigit = digitOn[3];
		endcase
	 end
	 
	 assign anode = anReg;
	 assign dot = ~(|(dot & ~anReg));
	 
	 reg [6:0] segReg;
	 assign segs = enableDigit ? segReg : 7'b0;
	 
	 always @(*) begin
		case(selectedData)
			4'h0: segReg = 7'b1000000;
			4'h1: segReg = 7'b1111001;
			4'h2: segReg = 7'b0100100;
			4'h3: segReg = 7'b0110000;
			4'h4: segReg = 7'b0011001;
			4'h5: segReg = 7'b0010010;
			4'h6: segReg = 7'b0000010;
			4'h7: segReg = 7'b1111000;
			4'h8: segReg = 7'b0000000;
			4'h9: segReg = 7'b0011000;
			4'hA: segReg = 7'b0001000;
			4'hB: segReg = 7'b0000011;
			4'hC: segReg = 7'b1000110;
			4'hD: segReg = 7'b0100001;
			4'hE: segReg = 7'b0000110;
			4'hF: segReg = 7'b0001110;
		endcase
	 end


endmodule
